Spirent TestCenter: Why I can change the clock source on some ports but others are showing me an error?

Doc ID    KNI16148
Version:    7.0
Status:    Published
Published date:    06/30/2020
Created Date:    06/25/2020


When you reserve individually the first port of each physical group on a card you can change clock source from Internal to internal w/PPM adj and backwards, however trying the same but this time you reserve individually the second port of each physical port and try to change the clock source mode, the GUI throws and error  saying:

must reserve all ports within these physical port groups (1-8) in order to set Internal PPM Adjustment


  • Clock source
  • Internal
  • Internal w/PPM Adjustment
  • Physical Port group


This is an expected behavior, the explanation is as follows:
  • First of all is important to clarify that although each port on a card is reservable individually (Depending on the card), they could be physically in "X" port physical port groups.
  • i.e. FX3-QSFP28-6 has 3 physical port groups of 2 ports each:
  • So, the clock settings apply to each physical port group because they share the same clock source. This could mean a singular PHY device or multiple PHY devices get the same clock signal.  Therefore any change to the frequency of the source to your PPM tuning will affect all physical ports of those PHYs.  This requirement is especially true for sub-rate speeds – i.e. splitting a high-speed PHY into many lower-speed links.
  • There is one master bus interface to the PHY device.  HW allows the firmware on the first physical port in the port group to be the driver.  The rest of the ports are not allowed access to the bus to prevent contention and corruption.  The driver handles the settings for the “slave” ports via internal messaging or files.
  • Currently the clock source settings becomes to defult (Internall) when releasing the ports/disconnecting from the chassis. and explanation of that is as follows:
    • On a port release, FW will put the HW back into default state.  This includes resetting the clock to internal mode.  On a release, you’ll see the GUI switch to internal to reflect the change being made to HW.  All cards are set to the default state on a port release.
    • Since HW only allows for PPM adjust per port group, FW/BLL has put restrictions.
    • The rules are that only one user can be on the port group and at least the primary port needs to be reserved when there’s any change to the clock source.

Root Cause

  • Expected behavior

Find Answers

Specified Languages

Please Sign In


Did you forget your password?
Click here for assistance

New user? Start here.